In recent years, several disclosed semiconductor devices comprise a plurality of stacked semiconductor chips in step with the trend of higher integration of circuits incorporated in semiconductor devices.
For example, Non-Patent Document 1 discloses a semiconductor device which comprises semiconductor chips, each formed with through vias and bumps, stacked one on another, where signals are transmitted and power is supplied between the stacked semiconductor chips.
On the other hand, Patent Documents 1, 2 and Non-Patent Document 2 disclose semiconductor devices which employ a non-contact interface circuit for transmitting signals between stacked semiconductor chips using coils formed in each semiconductor chip without using contact means such as through vias, bumps and the like.
In these semiconductor devices, a coil that is formed in one semiconductor chip generates a magnetic field signal, while a coil that is formed in another semiconductor chip receives the magnetic field signal, thereby transmitting signals between chips in a non-contact manner. In the following, the respective devices will be described in detail.
FIG. 1 is a schematic cross-sectional view of a semiconductor device described in Patent Document 1. This semiconductor device is formed with electromagnetic induction coil 102 or 103 on the surfaces of semiconductor chips 100 and 101. Semiconductor chips 100 and 101 are electromagnetically coupled by coils 102 and 103. In this regard, each coil 102 and 103 is provided with ferromagnetic material film 104 or 105 for enhancing a coupling coefficient between coils 102 and coil 103.
Patent Document 1 describes that the semiconductor device can be readily adapted to higher integration and an increase in the number of pins because the coils can be formed using highly accurate film deposition technologies such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), sputtering and the like.
Patent Document 1 also describes that since no solder is used, it is possible to eliminate the influence of circuit malfunctions due to the alpha beam.
Patent Document 1 further describes that a characteristic test is conducted after a semiconductor chip has been assembled, and a circuit chip can be readily decomposed and reassembled after confirming the characteristics without using thermal treatments and the like, and the yield rate is expected to increase.
FIG. 2 is a schematic cross-sectional view of a semiconductor device described in Patent Document 2. This semiconductor device comprises a stack of semiconductor chip Ln, which is provided with a transmission device S and a transmission coil SPS connected thereto, and semiconductor chip Ln+x that is provided with reception device E and reception coil SPE connected thereto. This semiconductor device transmits a signal between transmission coil SPS and reception coil SPE.
Patent document 2 describes that this semiconductor device can directly and reliably transmit a signal from the interior of one chip into the interior of an adjoining chip in a direction perpendicular to the chip without imposing extremely high requirements to make mutual adjustments and to ensure surface flatness between respective semiconductor chips.
FIG. 3 is a schematic perspective view of a semiconductor device described in Non-Patent Document 2. In this semiconductor device, a plurality of semiconductor chips 300, 301, 302 and 303 are stacked. Also, coils 304, 305 and 307 that are formed in the semiconductor chips are placed one on another at the same position in the vertical direction. Further, transmission circuit Tx and reception circuit Rx are disposed near the coils. With such a configuration, this semiconductor device transmits a signal between higher and lower semiconductor chips.
Non-Patent Document 2 describes that a low power consumption and broad band interface can be realized.    Non-Patent Document 1: John Baliga, “Chips Go Vertical”, IEEE Spectrum, March, pp. 35-39 (2004).    Patent Document 1: JP-7-221260A    Patent Document 2: JP-8-236696A    Non-Patent Document 2: Noriyaki Miura, et al., “Analysis and Design of Transceiver Circuit and Inductor Layout for Inductive Inter-chip Wireless Superconnect”, IEEE 2004 Symposium on VLSI Circuits Digest of Technical Papers, pp. 246-249 (2004).    Non-Patent Document 3: A. X. Widmer and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”, IBM J. Res. Develop., Vol. 27, No. 5, pp. 440-451, Sep. (1983)